Stacked power semiconductor device using dual lead frame and manufacturing method
US8436429B2 · kind B2 · utility
8Cited by
37References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2011 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Jun 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.