Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8436477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2012 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Apr 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The microelectronic element can include a plurality of stacked electrically interconnected semiconductor chips. The substrate can have contacts facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.