Power supply induced signal jitter compensation
US8436670B2 · kind B2 · utility
7Cited by
9References
19Claims
0Family size
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Key dates
| Filing date | Jan 13, 2011 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Mar 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.