System and method for level shifter
US8437175B2 · kind B2 · utility
1Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2012 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Feb 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.