Shared bit line SMT MRAM array with shunting transistors between the bit lines
US8437181B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 29, 2010 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Dec 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.