3D two bit-per-cell NAND flash memory
US8437192B2 · kind B2 · utility
52Cited by
10References
13Claims
0Family size
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Key dates
| Filing date | May 21, 2010 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Feb 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.