Patent · US Active

Secure design-for-test scan chains

US8438436B1 · kind B1 · utility

10Cited by

2References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Matthew Pond Baker · San Francisco, US
Weiguang Lu · San Jose, US

Key dates

Filing date	Jun 4, 2010
Grant date	May 7, 2013
Priority date	—
Expiry date	Jun 7, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318588
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC) can include placing the programmable IC in an operational mode and responsive to a request to access a scan chain within the programmable IC, selectively enabling a secure mode within the programmable IC according to a configuration state of the programmable IC. Enabling secure mode within the programmable IC can provide access to the scan chain. Responsive to enabling the secure mode, the programmable IC can remain in the secure mode and be prevented from re-entering the operational mode until the programmable IC is power cycled.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.