Memory with extended charge trapping layer

US8441063B2 · kind B2 · utility

Assignee

• Spansion LLC. · US

Inventors

• Shenqing Fang · Fremont, US
• Tung-Sheng Chen · Cupertino, US
• Chun Chen · San Jose, US

Key dates

• Filing date: Dec 30, 2010
• Grant date: May 14, 2013
• Expiry date: Jan 3, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/30

Abstract

A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.