Patent · US Active

Semiconductor arrangement

US8441128B2 · kind B2 · utility

21Cited by

2References

26Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventor

Daniel Domes · Schwäbisch Hall, DE

Key dates

Filing date	Aug 16, 2011
Grant date	May 14, 2013
Priority date	—
Expiry date	Aug 16, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH02M7/003
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.