Magnetic random access memory (MRAM) layout with uniform pattern
US8441850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Jun 3, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.