Patent · US Active

Method and apparatus synchronizing integrated circuit clocks

US8443225B2 · kind B2 · utility

0Cited by
3References
22Claims
0Family size

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Key dates

Filing dateAug 13, 2012
Grant dateMay 14, 2013
Priority date
Expiry dateAug 13, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C7/1045
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.