Methods and systems with transaction-level lockstep
US8443230B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Oct 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction. In response to the first access transaction being a read transaction, the read transaction is not issued to the peripheral device until the second processor executes the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.