Coprocessor interface architecture and methods of operating the same
US8447957B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2006 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Apr 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.