High performance DRC checking algorithm for derived layer based rules
US8448097B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2011 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Aug 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Roughly described, a design rule data set includes rules on derived layers. The rules are checked by traversing the corners of physical shapes, and for each corner, populating a layout topology database with values gleaned from that corner location, including values involving derived layers. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations, including violations of design rules defined on derived layers. Violations are reported in real time during manual editing of the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, scanning in the direction of the edge orientations. Scans stop only at corner positions on physical layers, and populate the layout topology database with what information can be gleaned based on the current scan line, including information about derived layers. The scans need not reach corners simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.