Low temperature p+ silicon junction material for a non-volatile memory device
US8450710B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 27, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Jul 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
A method for forming a non-volatile memory device includes forming a dielectric material overlying a semiconductor substrate, forming a first wiring structure overlying the first dielectric material, depositing an undoped amorphous silicon layer, depositing an aluminum layer over the amorphous silicon layer at a temperature of about 450 Degrees Celsius or lower, annealing the amorphous silicon and aluminum at a temperature of about 450 Degrees Celsius or lower to form a p+ polycrystalline layer, depositing a resistive switching material comprising an amorphous silicon material overlying the polycrystalline silicon material, forming a second wiring structure comprising a metal material overlying the resistive switching material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.