Method for fabricating finFET with merged fins and vertical silicide

US8455313B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Veeraraghavan S. Basker · Schenectady, US
• Andres Bryant · South Burlington, US
• Huiming Bu · Millwood, US
• Wilfried E. Haensch · Somers, US
• Effendi Leobandung · Stormville, US
• Chung-Hsun Lin · White Plains, US
• Theodorus E. Standaert · Clifton Park, US
• Tenko Yamashita · Schenectady, US
• Chun-Chen Yeh · Clifton Park, US

Key dates

• Filing date: Sep 14, 2012
• Grant date: Jun 4, 2013
• Expiry date: Sep 14, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/024

Abstract

A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.