Methods of forming gate structure and methods of manufacturing semiconductor device including the same
US8455345B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 8, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Dec 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.