Semiconductor devices and methods of manufacturing the same
US8455359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Nov 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.