Memory write error correction circuit
US8456926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | May 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.