NAND logic word line selection
US8456946B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Jun 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.