Patent · US Active

Method and apparatus for testing of a memory with redundancy elements

US8458545B2 · kind B2 · utility

2Cited by

2References

31Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Tanmoy Roy · Mountain View, US
Harsh Rawat · Faridabad, IN
Swapnil Bahl · New Delhi, IN
Amit Chhabra · Noida, IN
Nitin Jain · San Diego, US
Jatin Fultaria · Rajkot, IN

Key dates

Filing date	Nov 29, 2010
Grant date	Jun 4, 2013
Priority date	—
Expiry date	Jul 26, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/024
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.