Cycle time reduction in data preparation

US8458631B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chi-Ta Lu · Ganzikeng, TW
• Jia-Guei Jou · New Taipei, TW
• Peng Chen · Tangxia, CN
• Dong-Hsu Cheng · Tainan, TW

Key dates

• Filing date: Aug 11, 2011
• Grant date: Jun 4, 2013
• Expiry date: Aug 11, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/398
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.