Circuit partitioning and trace assignment in circuit design
US8458639B2 · kind B2 · utility
8Cited by
18References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2012 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | May 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for designing at least one integrated circuit (IC). In one embodiment, the method comprises partitioning a circuit into portions that represent a partitioning solution and assigning traces to interconnect the portions to generate a trace assignment solution. The method further comprises optimizing the circuit through a modification of at least one of the partitioning solution and the trace assignment solution, the optimizing based on evaluating a design parameter which is based at least in part on the trace assignment solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.