Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation

US8461016B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• James Mathew · Boise, US
• Brett D. Lowe · Boise, US
• Yunjun Ho · Boise, US
• H. Jim Fulford · Austin, US
• Jie Sun · San Diego, US
• Zhaoli Sun · Boise, US

Key dates

• Filing date: Oct 7, 2011
• Grant date: Jun 11, 2013
• Expiry date: Dec 15, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/40
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.