Clock signal generators having a reduced power feedback clock path and methods for generating clocks
US8461889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2010 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Apr 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.