Memory device with area efficient power gating circuitry
US8462562B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2011 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Mar 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.