Flash memory programming power reduction
US8462564B1 · kind B1 · utility
3Cited by
40References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2011 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Sep 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.