Address caching stored translation
US8464021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2008 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Dec 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.