Memory device and method thereof
US8464130B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Mar 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.