Power domain controller with gated through silicon via having FET with horizontal channel
US8466024B2 · kind B2 · utility
4Cited by
2References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2010 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Dec 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.