Method of forming metal interconnect structures in ultra low-k dielectrics
US8466056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Nov 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.