Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs

US8466473B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jin Cai · Somers, US
• Xiangdong Chen · Irvine, US
• Xinlin Wang · Irvine, US

Key dates

• Filing date: Dec 6, 2010
• Grant date: Jun 18, 2013
• Expiry date: Aug 11, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0191

Abstract

A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.