Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET
US8466501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2010 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Jul 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/149
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.