Chip-scale package
US8466546B2 · kind B2 · utility
2Cited by
46References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2006 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Mar 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.