High-reliability memory
US8468419B2 · kind B2 · utility
4Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2009 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | May 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.