Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

US8468483B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Nathan C. Buck · Underhill, US
• Brian M. Dreibelbis · Underhill, US
• John P. Dubuque · Jericho, US
• Eric A. Foreman · Saint Albans, US
• Peter A. Habitz · South Burlington, US
• Jeffrey G. Hemmett · South Burlington, US
• Natesan Venkateswaran · Hopewell Junction, US
• Chandramouli Visweswariah · Croton-on-Hudson, US
• Xiaoyue Wang · Santa Clara, US
• Vladimir Zolotov · Putnam Valley, US

Key dates

• Filing date: Oct 24, 2011
• Grant date: Jun 18, 2013
• Expiry date: Oct 24, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.