Method for designing stressor pattern
US8470655B1 · kind B1 · utility
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10Claims
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Key dates
| Filing date | Apr 18, 2012 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Apr 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A method for designing a stressor pattern is described, wherein the stressor pattern is used to form S/D regions of a second-type MOS transistor. A first distance between a boundary of the stressor pattern and a first active area of a first-type MOS transistor is derived. If the first distance is less than a safe distance, the stressor pattern is shrunk to make the first distance at least equal to the safe distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.