Resistive memory devices including vertical transistor arrays and related fabrication methods
US8471232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Nov 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
Abstract
A resistive memory device includes a vertical transistor and a variable resistance layer. The vertical transistor includes a gate electrode on a surface of a substrate, a gate insulation layer extending along a sidewall of the gate electrode, and a single crystalline silicon layer on the surface of the substrate adjacent to the gate insulation layer. At least a portion of the single crystalline silicon layer defines a channel region that extends in a direction substantially perpendicular to the surface of the substrate. The variable resistance layer is provided on the single crystalline silicon layer. The variable resistance layer is electrically insulated from the gate electrode. Related devices and fabrication methods are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.