Non-volatile memory and manufacturing method thereof
US8471328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jan 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.