Integrated circuits formed on strained substrates and including relaxed buffer layers and methods for the manufacture thereof

US8471342B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stefan Flachowsky · Dresden, DE
• Jan Hoentschel · Dresden, DE

Key dates

• Filing date: Dec 9, 2011
• Grant date: Jun 25, 2013
• Expiry date: Jan 3, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

Embodiments of a method for producing an integrated circuit are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes providing a strained substrate having an n-active region and a p-active region, etching a cavity into one of the n-active region and the p-active region, embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer having a strain orientation opposite that of the strained substrate, and fabricating n-type and t-type transistors over the n-active and p-active regions, respectively. The channel of the n-type transistor extends within one of the strained substrate and the body of strain material, while the channel of the p-type transistor extends within the other of the strained substrate and the body of strain material.