Inventor · Dresden, DE

Stefan Flachowsky

109Patents
9h-index
36Co-inventors
72Inventor score

Filing activity: May 21, 2010 → Jan 8, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US9224840B2 Replacement gate FinFET structures with high mobility channel Electricity 27 Active
US9425318B1 Integrated circuits with fets having nanowires and methods of manufacturing the same Electricity 24 Active
US8936977B2 Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Electricity 18 Active
US8703578B2 Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Electricity 18 Active
US8975704B2 Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Electricity 16 Active
US8912606B2 Integrated circuits having protruding source and drain regions and methods for forming integrated circuits Electricity 14 Active
US8574981B2 Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same Electricity 12 Active
US9515155B2 E-fuse design for high-K metal-gate technology Electricity 9 Active
US9865608B2 Method of forming a device including a floating gate electrode and a layer of ferroelectric material Electricity 9 Active
US8722500B2 Methods for fabricating integrated circuits having gate to active and gate to gate interconnects Electricity 9 Active
US9391176B2 Multi-gate FETs having corrugated semiconductor stacks and method of forming the same Electricity 7 Active
US8524563B2 Semiconductor device with strain-inducing regions and method thereof Electricity 7 Active
US9214396B1 Transistor with embedded stress-inducing layers Electricity 6 Active
US8471342B1 Integrated circuits formed on strained substrates and including relaxed buffer layers and methods for the manufacture thereof Electricity 6 Active
US8501601B2 Drive current increase in field effect transistors by asymmetric concentration profile of alloy species of a channel semiconductor alloy Electricity 6 Active
US9012956B2 Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe Electricity 6 Active
US9012277B2 In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices Electricity 6 Active
US8598007B1 Methods of performing highly tilted halo implantation processes on semiconductor devices Electricity 5 Active
US8835936B2 Source and drain doping using doped raised source and drain regions Electricity 5 Active
US9449972B1 Ferroelectric FinFET Electricity 4 Active
US9023713B2 Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same Electricity 4 Active
US8536034B2 Methods of forming stressed silicon-carbon areas in an NMOS transistor Electricity 4 Active
US8835255B2 Method of forming a semiconductor structure including a vertical nanowire Electricity 4 Active
US8524566B2 Methods for the fabrication of integrated circuits including back-etching of raised conductive structures Electricity 4 Active
US8698243B2 Semiconductor device with strain-inducing regions and method thereof Electricity 3 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.