Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8471394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Oct 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.