Detection of the zero crossing of the load current in a semiconductor device
US8471600B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Sep 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/13
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement includes a reverse conducting transistor having a gate electrode and a load current path between an emitter and collector electrode. The transistor is configured to allow for conducting a load current in a forward direction and in a reverse direction through the load current path and activated or deactivated by a respective signal at the gate electrode. The circuit arrangement further includes a gate control unit and a monitoring unit. The gate control unit is connected to the gate electrode and configured to deactivate the transistor or prevent an activation of the transistor via the gate electrode when the transistor is in a reverse conducting state. The monitoring unit is configured to detect a sudden rise of a collector-emitter voltage of the reverse conducting transistor which occurs, when the load current crosses zero, while the transistor is deactivated or activation is prevented by the gate control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.