Stacked semiconductor chip device with thermal management
US8472190B2 · kind B2 · utility
14Cited by
7References
24Claims
0Family size
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Key dates
| Filing date | Sep 24, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jun 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/1056
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing is provided that includes placing a thermal management device in thermal contact with a first semiconductor chip of a semiconductor chip device. The semiconductor chip device includes a first substrate coupled to the first semiconductor chip. The first substrate has a first aperture. At least one of the first semiconductor chip and the thermal management device is at least partially positioned in the first aperture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.