Nonvolatile memory and method for improved programming with reduced verify
US8472257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Dec 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.