Manufacturing method of flash memory structure with stress area

US8476156B1 · kind B1 · utility

Assignee

• EON Silicon Solution Inc. · TW

Inventors

• Yider Wu · Campbell, US
• Hung-Wei Chen · Zhubei City, TW

Key dates

• Filing date: Dec 28, 2011
• Grant date: Jul 2, 2013
• Expiry date: Dec 28, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/681

Abstract

In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.