DRAM layout with vertical FETS and method of formation
US8482047B2 · kind B2 · utility
18Cited by
124References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2012 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Sep 10, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/908
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.