Fan-out chip scale package
US8482136B2 · kind B2 · utility
0Cited by
8References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Nov 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.