Predictive modeling of contact and via modules for advanced on-chip interconnect technology
US8483997B2 · kind B2 · utility
3Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Aug 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.