Sequential digital circuitry with test scan

US8484523B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Ravindraraj Ramaraju · Round Rock, US
• Prashant U. Kenkare · Austin, US
• Gary A. Mussemann · Austin, US
• Mihir S. Sabnis · Austin, US

Key dates

• Filing date: Mar 23, 2010
• Grant date: Jul 9, 2013
• Expiry date: Jun 22, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318575
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.